Complementary Metal Oxide Semiconductor (CMOS) technology has for many years led the semiconductor industry in the fabrication of reliable and low-cost Integrated Circuits (ICs). The remarkable development of this technology is continuously evolving to fabricate smaller and faster devices for Very Large Scale Integration (VLSI) systems. The technology advance has in turn increased the CMOS devices' reliability problems, reducing the lifetime of the ICs and making them more sensitive to damage in the early steps of the production and assembly processes.
The IC's sensitivity to Electrostatic Discharge (ESD) is one of the most critical reliability problems in the semiconductor industry. ESD is an event that transfers a high amount of charge from one object (e.g., human body, transmission lines, or metallic pieces) to the other (e.g., microchip) in a relatively short period of time. The process results in an abrupt peak of current that can cause severe damage in the microchip.
ICs are required to pass testing to specific ESD standards. The standards define the typical waveform obtained during a particular type of ESD event. Each standard defines the characteristics of the rise time and decay time. In addition, the maximum peak of the ESD event can be defined to include the expected stress during the IC assembly, the type of application, and the final environment in which the IC is operating. The most widely use ESD standards are: 1) the human body model (HBM, charge transfers from human body to ground via the microchip); 2) the machine model (MM, charge transfers from a piece of equipment or metallic tool to ground via the microchip); 3) the charged device model (CDM, charge is built up on the microchip and transfers to ground); and 4) the system-level International Electrotechnical Commission standard for ESD immunity (e.g., IEC 1000-4-2, charge transfers from a charged capacitor through contact or air-gap discharge to ground via the microchip).
In the previous generations of micron- and sub-micron-level CMOS technologies, the IC ESD protection designs that comply with a required ESD standard have included schemes such as dual-diode I/O protection and a supply-clamp typically implemented with a Grounded-Gate Metal Oxide Semiconductor Field Effect Transistor (GGMOSFET). For some applications, both the I/O protection and the supply clamp are also implemented using different combinations of traditional devices, for instance a stack of zener diodes, medium voltage MOSFETs, Bipolar Junction Transistors (BJTs), and occasionally Silicon Controlled Rectifier (SCR)-type devices.
Some of the traditional ESD protection schemes can be migrated to a new generation of CMOS technology and still be effective in protecting particular applications. There are important complications though. The former ESD solutions typically cannot be readily scaled-down like the other components of an IC core circuit or migrated with the same sizes without paying an ESD performance penalty. For the newest CMOS technologies, the layout rules are stricter and the process characteristics are modified, such that the undesirable effects of the minimum feature size down-scaling are diminished. Nevertheless, these process improvements usually make the core circuit even more sensitive, and devices previously used for ESD protection may no longer be self-protected. Furthermore, the ICs are normally subjected by the customers to similar conditions and are required to comply with the same ESD standards as circuits in the former CMOS technologies.
Due to the ESD sensitivity of ICs in sub-micron CMOS technologies, devices for on-chip ESD protection can occupy a considerable area of the IC. Moreover, even increasing the size of the traditional protection structures to levels comparable with the core circuit dimensions does not guarantee that the ESD requirements are met. This condition creates a bottleneck for sub-micron IC development and diminishes the potential advantages of the CMOS scaling.
Limitations of typical ESD protection structures can be overcome by designing devices in which the current-voltage (I-V) characteristics show voltage snapback during an ESD event. These devices present a way to build smaller area I/O protection and supply clamps with very low leakage current during the normal operation of the circuit. The SCRs meet this characteristic, but the trigger voltage is very high and severe damage may occur in a sub-micron core circuit before the protection device triggers. The Low Voltage Trigger Silicon Controlled Rectifier (LVTSCR) triggers at relatively low voltages and it also shows snapback during the on-state. The LVTSCR has been used in the previous art for CMOS IC ESD protection, but it has the disadvantage that the holding voltage is very low and causes latchup problems in circuits where the I/O pad operation voltage is higher than about 1.2V. The High Holding Low Trigger Voltage Silicon Controlled Rectifier (HH-LVTSCR) allows tuning of the holding voltage in a wide range and at the same time keeps a relatively low trigger voltage.
The LVTSCRs and HH-LVTSCRs include a MOS (metal-oxide-semiconductor) structure that can modify the device's response during an ESD event and allows earlier triggering. Such devices in the previous art are safely used in CMOS technologies where they are self-protected and the gate of the devices can sustain the long-term voltage stress at the normal operating voltage, without reliability problems or degradation of the device characteristics. This assumption must be dismissed, however, for sub-micron CMOS applications which are required to pass a very high ESD voltage level, while operating to relatively high I/O voltages, close to- or exceeding- the level where the lifetime of the device is reduced by the effects of hot-carrier induced gate degradation.
Some alternatives have been previously discussed in the literature in order to overcome the gate reliability problem in the protection devices without degradation of the device's ESD performance. Solutions in prior art consider devices with a floating gate, sometimes referred to as devices with a dummy gate. However, these devices are highly dependent on the rise time and decay time of the ESD event as well as on temperature fluctuations. Results show that different versions of devices with floating gates exhibit characteristics that may cause a misleading interpretation of the device performance.
In a floating gate device, the conduction characteristics are unpredictably modified by the gate conditions. For instance, during an ESD event the gate MOS capacitor can become charged as a result of the ESD event. Since the gate voltage is not controlled, the charges underneath the gate are not immediately depleted back to the initial conditions and consequently the protection device can stay in the on-state. The leakage current through the channel of the protection device increases abruptly, leading to a circuit latchup, failure of the ESD protection, and/or further damage of the protected IC.
Thus, there is a need to overcome these and other problems of the prior art to obtain a protection device without gate reliability problems. Moreover, there is a need for sub-micron CMOS technology to be able to pass a high level of ESD current without latchup or damage. Further, there is a need for a device that can operate and protect against ESD during extreme temperature conditions, variable pulse rise times and pulse widths, and that is reliable during very extreme operating conditions.